Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1043 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Figure 33.27 Example of Serial Data Transmission in Clock Synchronous Mode from the Middle of
Transmission until Transmission Completion
Synchronization
clock
1 frame
Serial data
TXI interrupt
request
generated
TEI interrupt
request
generated
TXI interrupt
request
generated
TXI interrupt flag
(IRn in ICU*
1
)
Data written to TDR in
TXI interrupt handling
routine
SSR.TEND flag
(TIE = 1)
(TIE = 0)
Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 Bit 0
Bit 1 Bit 7
Data written to TDR in TXI
interrupt handling routine
(Set the TIE bit to 0 and the
TEIE bit to 1 after writing the
last data)
Note 1. Refer to section 15, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.

Renesas RX Series Specifications

General

Core	RXv1, RXv2, RXv3
Flash Memory	Up to 8 MB
RAM	Up to 1 MB
Operating Voltage	1.62V to 5.5V
Operating Temperature	-40°C to +85°C or +105°C
Package	BGA, LQFP
ADC Resolution	12-bit
DAC Resolution	12-bit
Communication Interfaces	SCI, SPI, I2C, USB, Ethernet, CAN
Architecture	32-bit
Security Features	Memory Protection Unit (MPU)