Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1044 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Figure 33.28 Example Flowchart of Serial Transmission in Clock Synchronous Mode
No
End
Yes
Initialization
Start transmission
Write transmit data to TDR
No
Yes
No
Yes
Set bits TIE, TE, and TEIE in SCR to 0
TXI interrupt
All transmit data written?
TEI interrupt
[ 1 ]
[ 2 ]
[ 3 ]
Set the SCR.TIE bit to 0, and
set the SCR.TEIE bit to 1
[ 1 ] SCI initialization:
Set data transmission.
[ 2 ] Writing transmit data write to TDR by a TXI interrupt
request:
When transmit data is transferred from TDR to TSR, a
transmit data empty interrupt (TXI) request is
generated.
Transmit data is written to TDR once from the handling
routine for TXI requests.
[ 3 ] Serial transmission continuation procedure:
To continue serial transmission, write transmit data to
TDR upon accepting a transmit data empty interrupt
(TXI) request. Transmit data can also be written to TDR
by activating the DMAC or DTC by the TXI interrupt
request.
When TEI interrupt requests are in use, set the
SCR.TIE bit to 0 and the SCR.TEIE bit to 1 after the last
of the data to be transmitted are written to the TDR.
Note: When the external clock is in use (the value of the SCR.CKE[1:0] bits is 10b or 11b), the rising edge on the SCK pin for
the last bit sets the SSR.TEND flag to 1. Setting the SCR.TE bit to 0 immediately after this may lead to insufficient
received-data hold time on the receiver side.

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English