R01UH0823EJ0100 Rev.1.00 Page 528 of 1823
Jul 31, 2019
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a)
(1) Example of Buffer Operation Setting Procedure
Figure 23.16 shows an example of the buffer operation setting procedure.
Figure 23.16 Example of Buffer Operation Setting Procedure
(2) Examples of Buffer Operation
(a) When TGR register is an Output Compare Register
Figure 23.17 shows an operation example in which PWM mode 1 has been designated for MTU0, and buffer operation
has been designated for registers TGRA and TGRC. The settings used in this example are TCNT clearing by compare
match B, high output at compare match A, and low output at compare match B. In this example, the TBTM.TTSA bit is
set to 0.
As buffer operation has been set, when compare match A occurs, the output changes and the value in buffer register
TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare
match A occurs.
For details of PWM modes, refer to
section 23.3.5, PWM Modes.
Figure 23.17 Example of Buffer Operation (1)
[1]
[2]
[3]
[1] Designate the TGR register as an input capture
register or output compare register by means of the
TIOR register.
[2] Designate the TGR register for buffer operation with
TMDR.BFA bit, TMDR.BFB bit, and TMDR.BFE bit.
[3] Set the TSTR.CSTn bit to 1 to start the count
operation.
Buffer operation
Select TGR function
Set buffer operation
Start count
Buffer operation
TCNT value
Time
0200h
0520h
0200h
0450h
0520h
0450h
0450h0200h
Transfer
0000h
MTIOC0A
MTU0.TGRB
MTU0.TGRC
MTU0.TGRA
MTU0.TGRA
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