126 Chapter2
Adjustment Procedures
19. 16 MHz PLL Adjustment
19. 16 MHz PLL Adjustment
NOTE This adjustment applies only to spectrum analyzers with A2 controller
assemblies other than 08563-60017.
Assembly Adjusted
A2 controller assembly
Related Performance Tests
Sweep Time Accuracy Gate Delay Accuracy and Gate Length Accuracy
Delayed Sweep Accuracy Fast Sweep Time Accuracy (Option 007)
Description
In spectrum analyzers with serial prefix numbers greater than or equal
to 3310A, the 16MHz CPU clock is phase locked to the 10 MHz
reference. The output of the 16 MHz PLL loop integrator is adjusted for
a clock frequency of approximately 14.4 MHz with the loop unlocked.
This ensures that the CPU will still function and the display annotation
will be distorted but readable, even if the 10 MHz reference to A2 is
absent.
NOTE If necessary, perform the display adjustments after performing the
following adjustment.
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