Chapter 6 337
General Troubleshooting
Block Diagram Description
• adjust gain and gain-vs-frequency for digital resolution bandwidths
(1 Hz through 100 Hz)
A5 IF Assembly
The A5 IF assembly has four crystal filter poles, four LC filter poles,
and step gain amplifiers. The crystal filters provide resolution
bandwidths of 300 Hz to 10 kHz. The LC filters provide resolution
bandwidths of 30 kHz to 2 MHz. All filter stages are in series. PIN diode
switches bypass unwanted stages.
An automatic IF adjustment, in spectrum analyzer firmware, sets
center frequency and 3 dB bandwidth of all filter poles through varactor
and PIN diodes. The firmware also controls crystal-pole symmetry and
the step gain amplification.
ADC/Interface Section
The ADC/interface section is the link between the controller section and
the rest of the spectrum analyzer. It controls the RF, synthesizer, and IF
sections through address and data lines on the W2 control cable (analog
bus). Analog signals from these sections are monitored by the ADC
(analog to digital converter) circuit on the ADC/interface section.
The ADC/interface section includes the A3 interface assembly, A1A1
keyboard, and A1A2 RPG (front-panel knob). The A3 assembly includes
log expand, video filter, peak detector, track-and-hold, real-time DACs,
RF gain DACs, +10 V reference, and ADC circuitry. The digital section
includes ADC ASM, sweep trigger, keyboard interface, RPG interface,
and analog bus interface circuitry.
ADC
The HP 8560E/EC spectrum analyzer can digitize signals with either
the main ADC on the A3 interface assembly or with fast ADC circuitry,
which is available as a standard feature, located on the A2 controller
board, on 8560EC instruments, and is available as an option, located on
the A16 board (Option 007) on 8560E instruments. The main ADC is
used for digitizing video signals when the sweep time is ≥30 ms and
various other signals, such as PLL error voltages. The fast ADC is used
only to digitize video signals for sweep times <30 ms.
Main ADC (part of A3)
For sweep times ≥30 ms, the spectrum analyzer uses a successive
approximation type of ADC. The main ADC has 10-bit resolution but it
is realized with 12-bit hardware. The ADC algorithmic state machine
(ADC ASM) controls the interface between the start/stop control and
the ADC, switching between positive and negative peak detectors when
the NORMAL detector mode is selected, and switching the ramp
counter into the ADC for comparison to the analog sweep ramp.
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