Page 7.3 - 18 COMBIVERT F5-A, -E, -H © KEB, 2012-10
Digital in- and outputs
7.3.1 Summary description digital inputs ..................................................................................... 7.3 - 19
7.3.2 Input signals PNP / NPN selection (di.00) ............................................................................ 7.3 - 20
7.3.3 Setting of digital inputs by software (di.01, di.02) ..............................................................7.3 - 20
7.3.4 Input terminal state (ru.21), internal input state (ru.22) ......................................................7.3 - 21
7.3.5 Digitalnoiselter(di.03),fastdigitalnoiselter(di.23).....................................................7.3 - 22
7.3.6 Inversion of Inputs (di.04) .....................................................................................................7.3 - 22
7.3.7 Delay activation / deactivation digital inputs ......................................................................7.3 - 22
7.3.8 Input trigger (di.05) ................................................................................................................7.3 - 23
7.3.9 Strobe-dependent Inputs (di.06, di.07, di.08) .......................................................................7.3 - 24
7.3.10 Reset / input selection (di.09) and reset / input slope selction (di.10) .............................. 7.3 - 25
7.3.11 Assignment of the inputs ...................................................................................................... 7.3 - 25
7.3.12 Software-ST and locking of the control release ..................................................................7.3 - 29
7.3.13 Deactivation of the digital control release ...........................................................................7.3 - 30
7.3.14 Short description - digital outputs ......................................................................................7.3 - 31
7.3.15 Output signals / hardware ..................................................................................................... 7.3 - 32
7.3.16 Outputlter(do.43,do.44) ....................................................................................................7.3 - 32
7.3.17 Switching Conditions (do.00...do.07) ...................................................................................7.3 - 32
7.3.18 Invertingofswitchingconditionsforags0...7(do.08...do.15) ........................................7.3 - 38
7.3.19 Selectionofswitchingconditionsforags0...7(do.16...do.23) ........................................7.3 - 39
7.3.20 AND/OR connections of the switching conditions (do.24) ...............................................7.3 - 39
7.3.21 Invertingofags(do.25...do.32) ........................................................................................... 7.3 - 39
7.3.22 Selectionofags(do.33...do.40) ..........................................................................................7.3 - 40
7.3.23 AND connection for outputs (do.41) ....................................................................................7.3 - 40
7.3.24 Output terminal state (ru.25) and digital output state (ru.80) ............................................7.3 - 41
7.3.25 Hardware output allocation (do.51) ...................................................................................... 7.3 - 42
7.3.26 Programming example ..........................................................................................................7.3 - 42