------------------------------------------------------------------------------
0 0/1 /0 0 MPLS e024-7f98-a21b - 9343 8192 TOE
------------------------------------------------------------------------------
Total: 1
14.4.5.5 Configuring Clock Synchronization
In this scenario, network-wide clock synchronization is implemented through synchronous
Ethernet clocks.
Prerequisites
l The clock daughter board CKMC/CKMD of the SCU control board is in position.
l The Ethernet upstream board is the GICK/GSCA (GE port) or X2CS/SPUF (10GE port)
board.
l The upstream MAN PSN of the OLT supports Synchronous Ethernet.
Data Plan
Item Data
Ethernet upstream
board
Port: 0/19/0
NOTE
The SPUF board exclusively occupies a service slot. This topic uses the GIU
upstream board as an example.
Procedure
l Configure the OLT-side clock.
1. Configure a system clock source.
Use the Ethernet line clock input from GIU port 0/19/0 as the system clock. Set the
index of the system clock to 0 and priority to 0 (highest priority).
huawei(config)#clock source 0 0/19/0
huawei(config)#clock priority system 0
2. Query the configurations and status of the system clock source.
Run the display clock source system command to query the configurations and status
of the clock source. Ensure that the configurations of the system clock source are
correct and the status of the system clock source is Normal.
huawei(config)#display clock source system
-------------------------------------------------------------------------
-----
Index Board Source Clk-type State Priority QL
Selected
-------------------------------------------------------------------------
-----
0 H801GICK 0/19/0 ETH Normal 0 ---
YES
-------------------------------------------------------------------------
-----
SmartAX MA5600T/MA5603T/MA5608T Multi-service
Access Module
Commissioning and Configuration Guide
14 FTTM Configuration (Base Station Access)
Issue 01 (2014-04-30) Huawei Proprietary and Confidential
Copyright © Huawei Technologies Co., Ltd.
1473
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