Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 118
UG586 November 30, 2016
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Native Interface Maintenance Command Signals
Table 1-54 lists the native interface maintenance command signals.
app_ref_req
When asserted, this active-High input requests that the Memory Controller send a refresh
command to the DRAM. It must be pulsed for a single cycle to make the request and then
deasserted at least until the app_ref_ack signal is asserted to acknowledge the request
and indicate that it has been sent.
app_ref_ack
When asserted, this active-High input acknowledges a refresh request and indicates that
the command has been sent from the Memory Controller to the PHY.
app_zq_req
When asserted, this active-High input requests that the Memory Controller send a ZQ
calibration command to the DRAM. It must be pulsed for a single cycle to make the request
and then deasserted at least until the app_zq_ack signal is asserted to acknowledge the
request and indicate that it has been sent.
app_zq_ack
When asserted, this active-High input acknowledges a ZQ calibration request and indicates
that the command has been sent from the Memory Controller to the PHY.
Table 1-54: Native Interface Maintenance Command Signals
Signal Direction Description
app_sr_req Input This input is reserved and should be tied to 0.
app_sr_active Output This output is reserved.
app_ref_req Input
This active-High input requests that a refresh command be issued to the
DRAM.
app_ref_ack Output
This active-High output indicates that the Memory Controller has sent
the requested refresh command to the PHY interface.
app_zq_req Input
This active-High input requests that a ZQ calibration command be issued
to the DRAM.
app_zq_ack Output
This active-High output indicates that the Memory Controller has sent
the requested ZQ calibration command to the PHY interface.
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