Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 575
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Core Architecture
This section describes the architecture of the 7 series FPGAs memory interface solutions
core, providing an overview of the core modules and interfaces.
Overview
The 7 series FPGAs memory interface solutions core is shown in Figure 4-44.
User FPGA Logic
The user FPGA logic block shown in Figure 4-44 is any FPGA design that requires to be
connected to an external LPDDR2 SDRAM. The user FPGA logic connects to the Memory
Controller through the user interface. An example user FPGA logic is provided with the core.
X-Ref Target - Figure 4-44
Figure 4-44: 7 Series FPGAs Memory Interface Solution
rst
clk
app_addr
app_cmd
app_en
app_hi_pri
app_wdf_data
app_wdf_end
app_wdf_mask
app_wdf_wren
app_rdy
app_rd_data
app_rd_data_end
app_rd_data_valid
app_wdf_rdy
app_sr_req
app_sr_active
app_ref_req
app_ref_ack
app_zq_req
app_zq_ack
ddr_ca
ddr_ck_n
ddr_cke
ddr_cs_n
ddr_dm
ddr_dq
ddr_dqs_n
ddr_dqs
User
FPGA
Logic
LPDDR2
SDRAM
User
Interface
Block
Memory
Controller
Physical
Layer
7 Series FPGAs Memory Interface Solution
User Interface
(1)
Physical Interface
7 Series FPGAs
Native Interface
MC/PHY Interface
ddr_ck
IOB
1. System clock (sys_clk_p and sys_clk_n/sys_clk_i), Reference clock (clk_ref_p and clk_ref_n/clk_ref_i), and system reset (sys_rst_n) port
connections are not shown in block diagram.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English