Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 633
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Bank Sharing Among Controllers
No unused part of a bank used in a memory interface is permitted to be shared with
another memory interface. The dedicated logic that controls all the FIFOs and phasers in a
bank is designed to only operate with a single memory interface and cannot be shared with
other memory interfaces.
Pin Swapping
• Pins can be freely swapped within each byte group (data and address/control), except
for the DQS pair which must be on a clock-capable DQS pair and the CK, which must be
on a clock-capable DQS pair.
• Byte groups (data and address/control) can be freely swapped with each other.
• Pins in the address/control byte groups can be freely swapped within and between
their byte groups.
• No other pin swapping is permitted.
Internal V
REF
Internal V
REF
can only be used for data rates of 800 Mb/s or below.
System Clock, MMCM Location, and Constraints
The MMCM is required to be in the bank that supplies the clock to the memory to meet the
specified interface performance. The system clock input is also strongly recommended to
be in this bank. The MIG tool follows these two rules whenever possible. The exception is a
16-bit interface in a single bank where there might not be pins available for the clock input.
In this case, the clock input needs to come from an adjacent bank through the frequency
backbone to the MMCM. The system clock input to the MMCM must come from clock
capable I/O.
The system clock input can only be used for an interface in the same column. The system
clock input cannot be driven from another column. The additional PLL or MMCM and clock
routing required for this induces too much additional jitter.
Unused outputs from the MMCM can be used as clock outputs. Only the settings for these
outputs can be changed. Settings related to the overall MMCM behavior and the used
outputs must not be disturbed.
A MMCM cannot be shared among interfaces.
See Clocking Architecture, page 585 for information on allowed MMCM parameters.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English