Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 400
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
• sys_rst – This is the asynchronous system reset input that can be generated internally
or driven from a pin. The MIG tool selects an appropriate I/O standard for the input
such as LVCMOS18 and LVCMOS25 for HP and HR banks, respectively. The default
polarity of sys_rst pin is active-Low. The polarity of sys_rst pin varies based on the
System Reset Polarity option chosen in FPGA Options page (Figure 3-20).
• init_calib_complete – This output indicates that the memory initialization and
calibration is complete and that the interface is ready to use. The
init_calib_complete signal is normally only used internally, but can be brought
out to a pin if desired.
• tg_compare_error – This output indicates that the traffic generator in the example
design has detected a data compare error. This signal is only generated in the example
design and is not part of the user design. This signal is not typically brought out to a
pin but can be, if desired.
Click Next to display the Summary page.
Summary
This page (Figure 3-24) provides the complete details about the memory core selection,
interface parameters, Vivado IP catalog options, and FPGA options of the active project.
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