Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 471
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Configuration
The XDC contains timing, pin, and I/O standard information. The sys_clk constraint sets
the operating frequency of the interface. It is set through the MIG GUI. This must be rerun
if this constraint needs to be altered, because other internal parameters are affected. For
example:
create_clock -period 1.875 [get_ports sys_clk_p]
The clk_ref constraint sets the frequency for the IDELAY reference clock, which is
typically 200 MHz. For example:
create_clock -period 5 [get_ports clk_ref_p]
The I/O standards are set appropriately for the RLDRAM II interface with LVCMOS15,
HSTL15_I, HSTL15_I_DCI, DIFF_HSTL15_I, or DIFF_HSTL15_I_DCI, as appropriate. LVDS_25 is
used for the system clock (sys_clk) and I/O delay reference clock (clk_ref). These
standards can be changed, as required, for the system configuration. These signals are
brought out to the top-level for system connection:
• sys_rst – This signal is the main system reset (asynchronous).
• init_calib_complete – This signal indicates when the internal calibration is done and
that the interface is ready for use.
• tg_compare_error – This signal is generated by the example design traffic generator if
read data does not match the write data.
These signals are all set to LVCMOS25 and can be altered as needed for the system design.
They can be generated and used internally instead of being brought out to pins.
Some interfaces might need to have the system clock in a bank above or below the bank
with the address/control and data. In this case, the MIG tool puts an additional constraint in
the XDC. For example:
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk_p]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hierarchical *pll*CLKIN1]
It results in the following warning during PAR. This warning can be ignored.
WARNING:Place:1402 - A clock IOB / PLL clock component pair have been found that are
not placed at an optimal clock IOB / PLL site pair. The clock IOB component
<sys_clk_p> is placed at site <IOB_X1Y76>. The corresponding PLL component
<u_backb16/u_infrastructure/plle2_i> is placed at site <PLLE2_ADV_X1Y2>. The clock
I/O can use the fast path between the IOB and the PLL if the IOB is placed on a Clock
Capable IOB site that has dedicated fast path to PLL sites within the same clock
region. You may want to analyze why this problem exists and correct it. This is
normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
<sys_clk_p.PAD> allowing your design to continue. This constraint disables all clock
placer rules related to the specified COMP.PIN. The use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended that this
error condition be corrected in the design.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English