Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 336
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
Write Calibration
When a write calibration is enabled for design that has memory frequency runs at 400 MHz
or above, the results of read calibration data alignment are used to determine if a given
setting is valid for correct write operation. After memory initialization, the read capture is
first calibrated using this set pattern before moving on to calibrate the writes. There is no
training register inside QDR II+ SRAM, the reads and writes cannot be independently
verified.
At each step of write calibration, the alignment of the read clock (CQ/CQB) with Q is
performed to ensure the correct capture of data. If the data alignment portion of read
calibration is performed for a given byte lane and the expected result is not found, the write
is assumed to have caused the failure. At each step of write calibration, the read calibration
and associated logic are reset and restarted.
Bit window size of data byte lane with K clock (K-byte lane) is first determined by using
PHASER_OUT stage 3 delay. Stage 3 tap starts increment from tap 0 until the left-edge is
found. If expected pattern return at tap 0, tap 0 is set as left edge tap position.
After the left edge of the K-byte lane is detected, the K clock is kept at this left tap position
to perform non-K-byte lanes alignment. All non-K-byte lanes are aligned to the left edge of
K-byte lane using the PHASER_OUT stage 2 delay.
Then, K clock (K-byte lane) is moved to the right using the PHASER_OUT stage 3 delay to
determine the aggregate right edge of all byte lanes. After the right edge of the data
window is determined, the centering process of K clock in the window is performed using
the PHASER_OUT stage3 delay.
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