Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 427
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Within the PHY, logic is broken up into read and write paths. The write path generates the
RLDRAM II/RLDRAM 3 signaling for generating read and write requests. This includes
clocking, control signals, address, data, and data mask signals. The read path is responsible
for calibration and providing read responses back to you with a corresponding valid signal.
For more details describing this process, see the Calibration section.
Client Interface
The client interface connects the 7 series FPGA user design to the RLDRAM II/RLDRAM 3
memory solutions core to simplify interactions between you and the external memory
device.
Command Request Signals
The client interface provides a set of signals used to issue a read or write command to the
memory device. These signals are summarized in Table 3-9.
Table 3-9: Client Interface Request Signals
Signal Direction Description
user_cmd_en Input
Command Enable. This signal issues a read or
write request and indicates that the
corresponding command signals are valid.
user_cmd[2 × CMD_PER_CLK – 1:0] Input
Command. This signal issues a read, write, or
NOP request. When user_cmd_en is asserted:
2’b00 = Write Command
2’b01 = Read Command
2’b10 = NOP
2’b11 = NOP
The NOP command is useful when more than
one command per clock cycle must be
provided to the Memory Controller yet not all
command slots are required in a given clock
cycle. The Memory Controller acts on the
other commands provided and ignore the
NOP command. NOP is not supported when
CMD_PER_CLK == 1. CMD_PER_CLK is a
top-level parameter used to determine how
many memory commands are provided to
the controller per FPGA logic clock cycle, it
depends on nCK_PER_CLK and the burst
length (see Figure 3-39)
user_addr[CMD_PER_CLK × ADDR_WIDTH – 1:0] Input
Command Address. This is the address to use
for a command request. It is valid when
user_cmd_en is asserted.
user_ba[CMD_PER_CLK × BANK_WIDTH – 1:0] Input
Command Bank Address. This is the address
to use for a write request. It is valid when
user_cmd_en is asserted.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English