Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 247
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Debug
•Verify DQS is toggling on the board. The FPGA sends DQS during Write Leveling. If DQS
is not toggling, something is wrong with the setup and the General Checks section of
this answer record should be thoroughly reviewed.
• Verify fly-by-routing is implemented correctly on the board.
•Verify CK to DQS trace routing. The CK clocks should be longer than DQS. The
recommended value for additional total electrical delay on CK/CK# relative to
DQS/DQS# is 150 ps, but any value greater than 0 ps is acceptable.
• The Mode Registers must be properly set up to enable Write Leveling. Specifically,
address bit A7 must be correct. If the part chosen in the MIG tool is not accurate or
there is an issue with the connection of the address bits on the board, this could be an
issue. If the Mode Registers are not set up to enable Write Leveling, the 0-to-1
transition is not seen.
Note:
For dual rank design when address mirroring is used, address bit A7 is not the same
between the two ranks.
• When dbg_wrlvl_err asserts (equals 1), users must determine during which of the
three different stages write leveling is performed the failure occurred. Set the ILA
trigger to dbg_wrlvl_err = R and look at the other “DDR Basic” signals to see which
stages completed.
a. If only PHASELOCK and DQSFOUND completed, the write leveling failure occurred
during the initial run through.
b. If dbg_wrcal_start did not assert, the write leveling failure occurred after
OCLKDELAYED calibration.
c. If dbg_wrcal_start asserted but dbg_wrcal_done did not, the write leveling
failure occurred during the final run through during Write Calibration.
• When dbg_wrlvl_done asserts (equals 1) and the results of each Write Leveling stage
is of interest, separately use the following three ILA triggers to capture the Write
Leveling tap results for each stage. Seeing how Write Leveling completed is useful to
see how far apart the taps are for different DQS byte groups.
a. dbg_wrlvl_done = R
b. dbg_wrcal_start = R
c. init_calib_complete = R
• To capture the write leveling results at each stage, change/increment dbg_dqs on the
VIO and set the appropriate trigger as noted above. Look at the taps results and record
in the “7 Series DDR3 Calibration Results” spreadsheet. Later releases of the MIG tool
include results for all DQS byte groups removing the need to use dbg_dqs.
Send Feedback

Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English