Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 234
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Calibration Stages
Memory Initialization
The PHY executes a JEDEC-compliant DDR2 or DDR3 initialization sequence following the
deassertion of system reset. Each DDR2 or DDR3 SDRAM has a series of mode registers
accessed through Mode Register Set (MRS) commands. These mode registers determine
various SDRAM behaviors, such as burst length, read and write CAS latency, and additive
latency. The MIG 7 series designs does not issue a calibration failure during Memory
Initialization.
All other initialization/calibration stages are reviewed in the following Debugging
Calibration Stages section.
X-Ref Target - Figure 1-97
Figure 1-97: Calibration Stages
DDR2/DDR3 SDRAM Initialization
System Reset
Phaser_IN Phase Lock (Phase Locks Read DQS to
Internal, Free-Running Frequency Reference Clock)
Phaser_In DQSFOUND Calibration
Write Leveling (For DDR3 SDRAM Only)
Multi-Purpose Register (MPR) Read Leveling (Center Read
DQS in Read DQ Window Independent of Writes)
OCLKDELAYED Calibration (Center Write DQS in Write
DQ Window Using MMCM Phase Shift)
Write Calibration (Aligning Write DQS to the Correct CK/
CK# Edge)
PRBS Read Leveling (Read DQS Centering in Read DQ
Window with PRBS Pattern to Account for ISI Effects)
PHY Initialization and Calibration Complete
Read Leveling (Initial DQ Alignment to DQS and DQS
Centering in Read DQ Window)
Write level again
at the end of
OCLKDELAYED
calibration.
Back to write
leveling to add 1 to
2 tCK of delay to
handle early writes.
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