Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 150
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
• When second edge is not found, second_edge_taps are set to zero. However, the
algorithm computes the midpoint of the data window using 63 as the second edge tap
position because 63 is the maximum fine tap value and no edge was detected.
OCLKDELAYED Calibration
Write DQS is centered in the write DQ window using the PHASER_OUT stage 3 delay in this
stage of calibration. The starting stage 3 tap value ranges from 28 to 34 depending on the
memory clock frequency. There are three substages in this calibration stage performed on
a per byte basis:
• Stage 3 tap limit determination
• Detection of write DQ valid window edges
•Write DQS centering in the write data valid window
The DDR3 SDRAM JEDEC specification requires the write DQS to be within ±90° of CK
defined by the t
DQSS
specification. To avoid t
DQSS
violation during the edge detection,
stage left and right limits of stage 3 tap movement are determined in this substage. These
limits are calibrated using MMCM phase shift taps to optimize the calibration center point.
The start of this substage is triggered by lim_start. The output signals
lim2ocal_stg3_left_lim and lim2ocal_stg3_right_lim validated by lim_done
are input to the edge detection substage.
In the edge detection substage, the first step is decrementing stage 3 taps until either one
or more edges are found or the tap value reaches lim2ocal_stg3_left_lim. The stage
3 taps are then increased until one or more edges are found or the tap value reaches
lim2ocal_stg3_right_lim.
At the end of edge detection stage, the following signals indicate which edges are detected.
Figure 1-66 shows the names associated with the different edges.
• f2z – If asserted, this indicates that the left-edge of the rise window was detected and it
validates fuzz2zero as the tap value of the left-edge of the rise window.
• z2f – If asserted, this indicates that the right-edge of the rise window is detected and it
validates zero2fuzz as the tap value of the right-edge of the rise window.
• f2o – If asserted, this indicates that the left-edge of the fall window was detected and it
validates fuzz2oneeighty as the tap value of the left-edge of the fall window.
• o2f – If asserted, this indicates that the right-edge of the fall window was detected and
it validates oneeighty2fuzz as the tap value of the right-edge of the fall window.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English