Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 668
UG586 November 30, 2016
www.xilinx.com
Chapter 6
Upgrading the ISE/CORE Generator MIG
Core in Vivado
To upgrade the previous version of the Memory Interface Generator (MIG) IP cores which
are generated using either ISE
®
or CORE Generator™, tools cannot be upgraded in a direct
manner similar to other IPs. Here is the process to upgrade the ISE/CORE Generator MIG
core in Vivado
®
.
1. This requires the mig.prj file of the MIG core generated using ISE or CORE Generator.
2. Invoke Vivado with the same FPGA part settings that the earlier core is generated with.
3. Apply the following command in the Tcl Console of Vivado to create the IP:
create_ip -name mig_7series -version <latest version> -vendor xilinx.com -library ip
-module_name <component_name>
For example,
create_ip -name mig_7series -version 4.1 -vendor xilinx.com -library ip -module_name
mig_7series_0
4. Apply the following command to generate the core with the previous MIG project
settings:
set_property CONFIG.XML_INPUT_FILE {<absolute path of the old core mig.prj>}
[get_ips <ip_name>]
For example,
set_property CONFIG.XML_INPUT_FILE
{/proj/mig/users/coregen_core/mig_7series_v4_1/mig.prj} [get_ips mig_7series_0]
5. You can see the core created in the Hierarchy.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English