Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 174
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Transfers can be isolated with gaps of non-activity, or there can be long bursts with no gaps.
The user design can identify when a request is being processed and when it finishes by
monitoring the rd_data_en and wr_data_en signals. When the rd_data_en signal is
asserted, the Memory Controller has completed processing a read command request.
Similarly, when the wr_data_en signal is asserted, the Memory Controller is processing a
write command request.
When NORM ordering mode is enabled, the Memory Controller reorders received requests
to optimize throughput between the FPGA and memory device. The data is returned to the
user design in the order processed, not the order received. The user design can identify the
specific request being processed by monitoring rd_data_addr and wr_data_addr.
These fields correspond to the data_buf_addr supplied when the user design submits
the request to the native interface. Both of these scenarios are depicted in Figure 1-87.
The native interface is implemented such that the user design must submit one request at
a time and, thus, multiple requests must be submitted in a serial fashion. Similarly, the core
must execute multiple commands to the memory device one at a time. However, due to
pipelining in the core implementation, read and write requests can be processed in parallel
at the native interface.
User Refresh
See User Refresh for the UI. The feature is identical in the native interface.
User ZQ
See User ZQ for the UI. The feature is identical in the native interface.
Physical Layer Interface (Non-Memory Controller Design)
The MIG Physical Layer, or PHY, can be used without the Memory Controller. The PHY files
are located in the user_design/rtl/phy directory generated by the MIG tool. Also
needed are the infrastructure files located in user_design/rtl/clocking. The MIG
Memory Controller can be used as an example of how to interface to the PHY. The
user_design/rtl/ip_top/mem_intfc.v file shows a sample instantiation of the
Memory Controller and the PHY.
The PHY provides a physical interface to an external DDR2 or DDR3 SDRAM. The PHY
generates signal timing and sequencing required to interface to the memory device. It
contains clock-, address-, and control- generation logic, write and read datapaths, and state
logic for initializing the SDRAM after power-up. In addition, the PHY contains calibration
logic to perform timing training of the read and write datapaths to account for system static
and dynamic delays. At the end of calibration the PHY asserts the init_calib_complete signal
output to the Memory Controller. The assertion of this signal indicates that the Memory
Controller can begin normal memory transactions.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English