Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 553
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
user_design/rtl/ui
This directory contains the user interface code that mediates between the native interface
of the Memory Controller and user applications (Table 4-9).
<component name>/user_design/xdc
Table 4-10 lists the modules in the user_design/xdc directory.
ddr_phy_rdlvl This module contains the Read leveling Stage1 calibration logic.
ddr_phy_top This is the top-level module for the physical layer.
ddr_phy_wrlvl_off_delay.v This module sets up the command and write datapath delays.
ddr_bitslip.v
This module contains the shift registers and MUXes to compensate the
bitslip and align the read data.
ddr_phy_pd.v
This module contains the Phase detector logic to compensate any drift over
the voltage and temperature variations.
ddr_phy_pd_top.v
This module is the top instance of phy_pd. This is used to instantiate Phase
detector based on different calibration mode of parallel or sequential
detection.
ddr_phy_prbs_rdlvl.v
This module contains calibration logic to perform data valid window
detection and capture clock alignment using PRBS data pattern.
Notes:
1. All file names are prefixed with the MIG version number. For example, for the MIG 4.1 release module name of
ddr_byte_group_io in generated output is now mig_7series_v4_1_ddr_byte_group_io.
Table 4-9: Modules In user_design/rtl/ui Directory
Name
(1)
Description
ui_cmd.v This is the user interface command port.
ui_rd_data.v
This is the user interface read buffer. It reorders read data returned from the
Memory Controller back to the request order.
ui_wr_data.v This is the user interface write buffer.
ui_top.v This is the top-level of the Memory Controller user interface.
Notes:
1. All file names are prefixed with the MIG version number. For example, for the MIG 4.1 release module name of
ui_cmd in generated output is now mig_7series_v4_1_ui_cmd.
Table 4-10: Modules in user_design/xdc Directory
Name Description
<component_name>.xdc This is the XDC for the core and the user design.
Table 4-8: Modules in user_design/rtl/phy Directory (Cont’d)
Name
(1)
Description
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General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English