Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 589
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Bank Machines
Most of the Memory Controller logic resides in the bank machines. A given bank machine
manages a single DRAM bank at any given time. However, bank machine assignment is
dynamic, so it is not necessary to have a bank machine for each physical bank. The number
of banks can be configured to trade off between area and performance. This is discussed in
greater detail in the Precharge Policy section.
The duration of a bank machine assignment to a particular DRAM bank is coupled to user
requests rather than the state of the target DRAM bank. When a request is accepted, it is
assigned to a bank machine. When a request is complete, the bank machine is released and
is made available for assignment to another request. Bank machines issue all the commands
necessary to complete the request.
On behalf of the current request, a bank machine must generate row commands and
column commands to complete the request. Row and column commands are independent
but must adhere to DRAM timing requirements.
The following simplified example illustrates this concept. Consider the case when the
Memory Controller and DRAM are idle when a single request arrives. The bank machine at
the head of the pool:
1. Accepts your request
2. Activates the target row
3. Issues the column (read or write) command
4. Precharges the target row
5. Returns to the idle pool of bank machines
Similar functionality applies when multiple requests arrive targeting different rows or banks.
Now consider the case when a request arrives targeting an open DRAM bank, managed by
an already active bank machine. The already active bank machine recognizes that the new
request targets the same DRAM bank and skips the precharge step (step 4). The bank
machine at the head of the idle pool accepts the new user request and skips the activate
step (step 2).
Finally, when a request arrives in between both a previous and subsequent request all to the
same target DRAM bank, the controller skips both the activate (step 2) and precharge
(step 4) operations.
A bank machine precharges a DRAM bank as soon as possible unless another pending
request targets the same bank. This is discussed in greater detail in the Precharge Policy
section.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English