Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 667
UG586 November 30, 2016
www.xilinx.com
Chapter 5: Multicontroller Design
Directory Structure
The MIG output directory structure is slightly different for the user design RTL folder
compared with the single controller design. The user design RTL folder contains the
subfolders for each memory interface, and related RTL files are generated in the
corresponding memory interface folders. All chosen memory interfaces for multicontroller
designs are shown here.
mig_7series_v4_1
docs
example_design
par
rtl
traffic_gen
sim
synth
user_design
rtl
clocking
ddr3_sdram
controller
ecc
ip_top
phy
ui
qdriiplus_sram
phy
rldram_ii
controller
ip_top
phy
ui
xdc
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English