Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 172
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
To account for the worst case, subtract tRCD, CL, the data transit time and tRP for each bank
machine to ensure that all transactions can complete before the target tZQI expires.
Equation 1-2 shows the ZQ request interval maximum.
Equation 1-2
A user ZQ should be issued immediately following calibration to establish a time baseline
for determining when to send subsequent requests.
Native Interface
The native interface protocol is shown in Figure 1-85.
Requests are presented to the native interface as an address and a command. The address
is composed of the bank, row, and column inputs. The command is encoded on the cmd
input.
The address and command are presented to the native interface one state before they are
validated with the use_addr signal. The memory interface indicates that it can accept the
request by asserting the accept signal. Requests are confirmed as accepted when
use_addr and accept are both asserted in the same clock cycle. If use_addr is asserted
but accept is not, the request is not accepted and must be repeated. This behavior is shown
in Figure 1-86.
X-Ref Target - Figure 1-85
Figure 1-85: Native Interface Protocol
tZQI tRCD CL 4+()tCK×()+ tRP+()nBANK_MACHS×–()
5'?C??
CLK
RANKBANKROWCOLUMN
CMDHI?PRIORITY
ACCEPT
USE?ADDR
DATA?BUF?ADDR
WR?DATA?EN
WR?DATA?ADDR
RD?DATA?EN
RD?DATA?ADDR
RD?DATA
WR?DATA
WR?DATA?MASK
$n$ $n$
$n$ $n$
To Next Page
Loading...
Need help?
General
