Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 527
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Pin Compatible FPGAs
The Pin Compatible FPGAs page lists FPGAs in the selected family having the same
package. If the generated pinout from the MIG tool needs to be compatible with any of
these other FPGAs, this option should be used to select the FPGAs with which the pinout
has to be compatible (Figure 4-15).
Xilinx 7 series devices using stacked silicon interconnect (SSI) technology have Super Logic
Regions (SLRs). Memory interfaces cannot span across SLRs. If the device selected or a
compatible device that is selected has SLRs, the MIG tool ensures that the interface does
not cross SLR boundaries.
1. Select any of the compatible FPGAs in the list. Only the common pins between the target
and selected FPGAs are used by the MIG tool. The name in the text box signifies the
target FPGA selected.
2. Click Next to display the Memory Selection page.
X-Ref Target - Figure 4-15
Figure 4-15: Pin-Compatible 7 Series FPGAs
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English