Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 481
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Information on Sharing BUFG Clock (phy_clk)
The MIG 7 series RLDRAM II/RLDRAM 3 design includes an MMCM which outputs the
phy_clk on a BUFG route. It is not possible to share this clock amongst multiple
controllers to synchronize the user interfaces. This is not allowed because the timing from
the FPGA logic to the PHY Control block must be controlled. This is not possible when the
clock is shared amongst multiple controllers. The only option for synchronizing user
interfaces amongst multiple controllers is to create an asynchronous FIFO for clock domain
transfer.
Information on Sync_Pulse
The MIG 7 series RLDRAM II/RLDRAM 3 design includes one PLL that generates the
necessary design clocks. One of these outputs is the sync_pulse. The sync pulse clock is
1/16 of the mem_refclk frequency and must have a duty cycle distortion of 1/16 or 6.25%.
This clock is distributed across the low skew clock backbone and keeps all PHASER_IN/_OUT
and PHY_Control blocks in sync with each other. The signal is sampled by the mem_refclk
in both the PHASER_INs/_OUTs and PHY_Control blocks. The phase, frequency, and duty
cycle of the sync_pulse is chosen to provide the greatest setup and hold margin across
PVT.
Debugging RLDRAM II and RLDRAM 3 Designs
This section defines a step-by-step debugging procedure to assist in the identification and
resolution of any issues that might arise during each phase of the memory interface design
process.
Introduction
The RLDRAM II and RLDRAM 3 memory interfaces simplify the challenges associated with
memory interface design. However, every application environment is unique and proper
due diligence is required to ensure a robust design. Careful attention must be given to
functional testing through simulation, proper synthesis and implementation, adherence to
PCB layout guidelines, and board verification through IBIS simulation and signal integrity
analysis.
This section defines a step-by-step debugging procedure to assist in the identification and
resolution of any issues that might arise during each phase of the design process. Details
are provided on:
• Functional verification using the UNISIM simulation models
• Design implementation verification
•Board layout verification
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English