Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 333
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
Calibration
The calibration logic provides the required amount of delay on the read clock and read data
to align the clock in the center of the data valid window. The centering of the clock is done
using PHASERs which provide very fine resolution delay taps on the clock. Each PHASER_IN
fine delay tap increments the clock by 1/64
th
of the data period.
Calibration begins after the echo clocks are stable from the memory device. The amount of
time required to wait for the echo clocks to become stable is based upon the memory
vendor and should be specified using the CLK_STABLE parameter to the core. Prior to this
point, all read path logic is held in reset. Calibration is performed in two stages:
1. Calibration of read clock with respect to Q
2. Data alignment and valid generation
X-Ref Target - Figure 2-46
Figure 2-46: Read Datapath
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