Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 600
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
The PHY cmd field is set based on whether the sequence of two commands has either a
write, a read, or neither. The PHY cmd field is set to write if there is a write request in the
command sequence. It is set to read if there is a read request in the command sequence,
and it is set to non-data if there is neither a write nor a read request in the command
sequence. A write and a read request cannot be issued within a sequence of two commands.
The control offset field in the PHY control word defines when the command OUT_FIFOs is
read out and transferred to the IOLOGIC. The data offset defines when the data OUT_FIFOs
are read out with respect to the command OUT_FIFOs being read. For read commands, the
data offset is set to zero. The PHY control block assumes that valid data associated with a
write command is already available in the DQ OUT_FIFO when it is required to be read out.
Command Path
A command requested by the calibration logic or Memory Controller is sent out as a PHY
control word to the PHY control block and a simultaneous input to the
address/control/command OUT_FIFOs. Each of the address/control/command signals must
have values for two memory clock cycles because each PHY_Clk cycle entails two memory
clock cycles.
There are three types of commands:
• Write commands including write and write with auto precharge. The PHY command
values in the PHY control word for both these write commands are the same (0x01).
The difference is the address value input to the OUT_FIFO. Address bit CA[0] bit on
falling edge of CK is 1 for writes with auto precharge in the address OUT_FIFOs.
• Read commands including read and read with auto precharge. The PHY command
values in the PHY control word for both these read commands are the same (0x11). The
difference is the address value input to the OUT_FIFO. Address bit CA[0] bit on falling
edge of CK is 1 for reads with auto precharge in the address OUT_FIFOs.
• Non-Data commands including Mode Register Set, Refresh, Precharge, Precharge All
Banks, Activate, No Operation, and Deselect. The PHY command values in the PHY
control word for all these commands are the same (0x100). The ca value inputs to the
OUT_FIFOs associated with these commands differ.
Figure 4-50 shows the block diagram of the address/control/command path. The OSERDES
is used in single data rate mode because address/control/commands are DDR signals. A
PHY control word is qualified with the Phy_Ctl_Wr_N signal and an entry to the
OUT_FIFOs is qualified with the PHY_Cmd_WrEn signal. The FPGA logic need not issue NOP
commands during long wait times between valid commands to the PHY control block
because the default in the dedicated PHY for address/commands can be set to 0 or 1 as
needed.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English