Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 601
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
The timing diagram of the address/command path from the output of the OUT_FIFO to the
FPGA pins is shown in Figure 4-51.
X-Ref Target - Figure 4-50
Figure 4-50: Address/Command Path Block Diagram
Out_FIFO_B
D
WEn REn
Q
WClk RClk
Full
AF
AE
Empty
PHY_Clk
OSERDES
Byte Group
OF_RE_B
Phaser
Out B
OClk1x
OClk1x90
OClkDiv
PhaseRef
FreqRef
CTS[1:0]
DTS[1:0]
RdEnable
DQS[1:0]
RankSel[1:0]
Enable_Calib[1:0]
Burst_Pending
Phaser
In B
IClk1x
IClkDiv
PhaseRef
FreqRef
Enable_Calib[1:0]
Burst_Pending
RankSel[1:0]
RClk
WriteEnable
Out_FIFO_A
D
WEn REn
Q
WClk RClk
Full
AF
AE
Empty
In_FIFO_A
DQ
WClk
WEn REn
RClk
Full
AF
AE
Empty
OSERDES
Byte Group
OF_RE_A
Mem_Ref_Clk
Cmd Byte Group B
Cmd Byte Group A
In_FIFO_A
DQ
WClk
WEn REn
RClk
Full
AF
AE
Empty
RAS_N, CAS_N, WE_N, BA[2:0], A[15:12]
DDR_Clk_B
DDR_DivClk_B
A[11:0]
DDR_Clk_A
DDR_DivClk_A
PHY_CA[19:0],PHY_CS_N
PHY_Cmd_WrEn
PHY_Cmd_Full
PHY_Cmd_AlmostFull
0
1
Note: CK is implemented as an ODDR clocked by
DDR_Clkdelayed
ODDR Byte
Group B
BUFIO
DDR_DivR_Clk
From
PHY
Control
Block
From
PHY
Control
Block
From
PHY
Control
Block
From
PHY
Control
Block
DDR_Clkdelayed_B
OBUF
OBUF
OBUF
Phaser
In A
IClk1x
IClkDiv
PhaseRef
FreqRef
Enable_Calib[1:0]
Burst_Pending
RankSel[1:0]
RClk
WriteEnable
Phaser
Out A
OClk1x
OClk1x90
OClkDiv
PhaseRef
FreqRef
CTS[1:0]
DTS[1:0]
RdEnable
DQS[1:0]
RankSel[1:0]
Enable_Calib[1:0]
Burst_Pending
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English