Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 343
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
Bank Sharing Among Controllers
No unused part of a bank used in a memory interface is permitted to be shared with
another memory interface. The dedicated logic that controls all the FIFOs and phasers in a
bank is designed to only operate with a single memory interface and cannot be shared with
other memory interfaces. With the exception of the shared address and control in the dual
controller supported in MIG.
Trace Length Requirements
The trace lengths described here are for high-speed operation and can be relaxed
depending on the application target bandwidth requirements. The package delay should be
included when determining the effective trace length. Note that different parts in the same
package have different internal package skew values. De-rate the minimum period
appropriately in the MIG Controller Options page when different parts in the same
package are used.
One method for determining the delay is to use the L and C values for each pin from the IBIS
models. The delay value is determined as the square root of (L × C).
Another method is to generate the package lengths using the Vivado Design Suite. The
following commands generate a csv file that contains the package delay values for every
pin of the device under consideration.
link_design -part <part_number>
write_csv <file_name>
For example, to obtain the package delay information for the 7 series FPGA
XC7K160T-FF676, this command should be issued:
link_design -part xc7k160tfbg676
write_csv flight_time
This generates a file named flight_time.csv in the current directory with package trace
delay information for each pin. While applying specific trace-matching guidelines for the
QDR II+ SRAM interface, this additional package delay term should be considered for the
overall electrical propagation delay. Different die in the same package might have different
delays for the same package pin. If this is expected, the values should be averaged
appropriately. This decreases the maximum possible performance for the target device.
These rules indicate the maximum electrical delays between QDR II+ SRAM signals:
• The maximum electrical delay between any bit in the data bus, D, and its associated
K/K# clocks should be ±15 ps.
• The maximum electrical delay between any Q and its associated CQ/CQ# should be
±15 ps.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English