Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 244
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Debug
•If the DQSFOUND stage fails, probe DQS at the memory. Sets of four back-to-back reads
should be seen. Read DQS(s) is required by the PHASER_IN(s) to establish the
read_data_offset value. If the design is stuck in the DQSFOUND stage, start
observing the quality of DQS at the memory.
• Look at the read_data_offset values. There are two sets of read_data_offset
values that need to be compared.
°
To determine the read data offset found at the end of DQSFOUND calibration, look at
dbg_rd_data_offset_0, dbg_calib_data_offset_1 (only when more than
one bank is used), dbg_calib_data_offset_2 (only when three banks are used).
°
To determine the data offset used during normal operation reads, look at
dbg_data_offset, dbg_data_offset_1 (only when more than one bank is used),
and dbg_data_ofset_2 (only when three banks are used).
- These signals change between reads, writes, and non-data commands. During
writes, the value is CWL + 2 + slot#. During non-data commands, the value is 0.
During reads, the value should match what was found during DQSFOUND
calibration (dbg_rd_data_offset_0, dbg_rd_data_offset_1, and
dbg_rd_data_offset_2).
• Compare the read data offset values used during calibration and normal operation
reads. These values should match for reads with even CWL and be off by 1 for reads
with odd CWL. One additional offset is added for odd CWL values because reads/writes
are assigned to slot1 by the Memory Controller, whereas slot0 is used for even CWL.
• The read data offset should be equal to or greater than CL (Read Latency) + 4 or 5
memory cycles of round trip delay on the PCB. For DDR2 interfaces at lower
frequencies, it is possible for read data offset to equal CL (Read Latency).
• The PHASER_OUT stage 2 delay for CK/Address/Command/Control byte lanes should
also be observed for differences between passing and failing cases. The CK
PHASER_OUT stage 2 delay can be observed in Vivado logic analyzer using the
dbg_po_counter_read_val signal with dbg_pi_dqsfound_done as the trigger.
• When this stage fails (pi_dqsfound_err = 1), look to see if any of the
dbg_calib_rd_data_offset/_1/_2 have calculated offsets. If not, focus on the
DQS signals associated with the failing bank by probing each and analyzing the signal
integrity.
If pi_dqsfound_err asserted, denoting a failure during DQSFOUND calibration, use
pi_dqsfound_err = R as the trigger. If this stage completed successfully with the
asserting of pi_dqsfound_done = 1, use pi_dqsfound_done = R as the trigger to
analyze how the stage completed.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English