Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 77
UG586 November 30, 2016
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
2. The cmd_seed_i and data_seed_i input values are set for the internal PRBS
generator. This step is not required for other patterns.
3. The instr_mode_i input is set to the desired mode (PRBS is the default).
4. The bl_mode_i input is set to the desired mode (PRBS is the default).
5. The data_mode_i input should have the same value as in the memory pattern
initialization stage detailed in Memory Initialization.
6. The run_traffic_i input is asserted to start running traffic.
7. If an error occurs during testing (for example, the read data does not match the
expected data), the error bit is set until reset is applied.
8. Upon receiving an error, the error_status bus latches the values defined in Table 1-13,
page 73.
With some modifications, the example design can be changed to allow addr_mode_i,
instr_mode_i, and bl_mode_i to be changed dynamically when run_traffic_i is
deasserted. However, after changing the setting, the memory initialization steps need to be
repeated to ensure that the proper pattern is loaded into the memory space.
Note:
°
When the chip select option is disabled, the simulation test bench always ties the
memory model chip select bit(s) to zero for proper operation.
°
When the data mask option is disabled, the simulation test bench always ties the
memory model data mask bit(s) to zero for proper operation.
Simulating the Example Design (for Designs with the AXI4 Interface)
The MIG tool provides a synthesizable AXI4 test bench to generate various traffic patterns
to the Memory Controller. This test bench consists of an instance of user design (Memory
Controller) with AXI4 interface, a traffic_generator (axi4_tg) that generates traffic patterns
through the AXI4 interface of the controller as shown in Figure 1-41. The infrastructure
block inside the user design provides clock resources to both the controller and the traffic
generator. Figure 1-41 shows a block diagram of the example design test bench. The details
of the clocks in Figure 1-41 are provided in Clocking Architecture, page 119.
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