Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 537
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
• sys_clk – This is the system clock input for the memory interface and is typically
connected to a low-jitter external clock source. Either a single input or a differential
pair can be selected based on the System Clock selection in the FPGA Options page
(Figure 4-21). The sys_clk input must be in the same column as the memory
interface. If this pin is connected in the same banks as the memory interface, the MIG
tool selects an I/O standard compatible with the interface, such as DIFF_SSTL12 or
SSTL12. If sys_clk is not connected in a memory interface bank, the MIG tool selects
an appropriate standard such as LVCMOS18 or LVDS. The XDC can be modified as
desired after generation.
• clk_ref – This is the reference frequency input for the IDELAY control. This is a 200 MHz
input. The clk_ref input can be generated internally or connected to an external
source. A single input or a differential pair can be selected based on the System Clock
selection in the FPGA Options page (Figure 4-21). The I/O standard is selected in a
similar way as sys_clk.
• sys_rst – This is the asynchronous system reset input that can be generated internally
or driven from a pin. The MIG tool selects an appropriate I/O standard for the input
such as LVCMOS18 and LVCMOS25 for HP and HR banks, respectively. The default
polarity of sys_rst pin is active-Low. The polarity of sys_rst pin varies based on the
System Reset Polarity option chosen in FPGA Options page (Figure 4-21).
• init_calib_complete – This output indicates that the memory initialization and
calibration is complete and that the interface is ready to use. The
init_calib_complete signal is normally only used internally, but can be brought
out to a pin if desired.
• tg_compare_error – This output indicates that the traffic generator in the example
design has detected a data compare error. This signal is only generated in the example
design and is not part of the user design. This signal is not typically brought out to a
pin but can be, if desired.
Click Next to display the Summary page.
Summary
This page provides the complete details about the 7 series FPGA memory core selection,
interface parameters, Vivado tool options, and FPGA options of the active project
(Figure 4-25).
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English