Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 145
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
PHASER_IN Phase Lock
PHASER_IN is placed in the read calibration mode to phase align its free-running frequency
reference clock to the associated read DQS. The calibration logic issues back-to-back read
commands to provide the PHASER_IN block with a continuous stream of DQS pulses for it to
achieve lock. A continuous stream of DQS pulses is required for the PHASER_IN block to
phase align the free-running frequency reference clock to the associated read DQS. Each
DQS has a PHASER_IN block associated with it. When the PHASER_IN lock signal
(pi_phase_locked) of all the DQS PHASER_INs are asserted, the calibration logic
deasserts the read calibration signal to put the PHASER_INs in normal operation mode.
PHASER_IN DQSFOUND Calibration
This calibration stage is required to align the different DQS groups to the same PHY_Clk
clock edge in an I/O bank. Different DQS groups have different skews with respect to each
other because of the clock (CK) fly-by routing differences to each DDR2 or DDR3
component and delay differences in each component. This calibration stage is required to
determine the optimal position of read data_offset with respect to the read command
per I/O bank.
In this stage of calibration, the PHASER_IN block is in normal operation mode and the
calibration logic issues a set of four back-to-back read commands with gaps in between.
The data_offset associated with the first read command is not accurate because the
round-trip delays are unknown.
For interfaces using HP I/O banks, the data_offset for the first set of read commands is
set to CL + 13. The data_offset value for the subsequent set of reads is decreased one
memory clock cycle at a time until the DQSFOUND output from the PHASER_IN block is
asserted. When the DQSFOUND signal is asserted for all of the bytes, the CK delay stage
begins.
For interfaces using HR I/O banks, the data_offset for the first set of read commands is
set to CL – 2. The data_offset value for the subsequent set of reads is increased one
memory clock cycle at a time until the DQSFOUND output from the PHASER_IN block is
asserted. When the DQSFOUND signal is asserted for all of the bytes, the CK delay stage
begins.
In the CK delay stage, the PHASER_OUT stage 2 delay tap is increased one at a time starting
from 0 to 63 for CK/Address/Command/Control byte lanes. This effectively moves where the
read DQS preamble begins and causes the DQSFOUND to fail. Any one DQSFOUND failure of
the entire interface is considered a failure. A passing window is determined by recording the
taps where the DQSFOUND failures occur. The final tap value for
CK/Address/Command/Control byte lanes is set to the center of the passing window. If no
failing edges are found the final tap is set to 32.
Send Feedback

Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English