Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 379
UG586 November 30, 2016
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Chapter 3
RLDRAM II and RLDRAM 3 Memory
Interface Solutions
Introduction
The RLDRAM II and RLDRAM 3 Memory Interface Solutions (MIS) are a Memory Controller
and physical layer for interfacing Xilinx
®
7 series FPGAs user designs to RLDRAM II and
RLDRAM 3 devices. An RLDRAM II/RLDRAM 3 device can transfer up to two, four, or eight
words of data per request and are commonly used in applications such as look-up tables
(LUTs), L3 cache, and graphics.
The RLDRAM II/RLDRAM 3 memory solutions core is composed of a user interface (UI),
Memory Controller (MC), and physical layer (PHY). It takes simple user commands and
converts them to the RLDRAM II/RLDRAM 3 protocol before sending them to the memory.
Unique capabilities of the 7 series FPGAs allow the PHY to maximize performance and
simplify read data capture within the FPGA. The full solution is complete with a
synthesizable reference design.
This chapter describes the core architecture and information about using, customizing, and
simulating a LogiCORE™ IP RLDRAM II/RLDRAM 3 memory interface core for the 7 series
FPGAs.
Although this soft Memory Controller core is a fully verified solution with guaranteed
performance, termination and trace routing rules for PCB design need to be followed to
have the best design. For detailed board design guidelines, see Design Guidelines,
page 466.
IMPORTANT: RLDRAM II and RLDRAM 3 designs currently do not support memory-mapped AXI4
interfaces.
For detailed information and updates about the 7 series FPGAs RLDRAM II and RLDRAM 3
interface cores, see the appropriate 7 series FPGAs data sheet [Ref 13] and the Zynq-7000
AP SoC and 7 Series FPGAs Memory Interface Solutions Data Sheet (DS176) [Ref 1].
IMPORTANT: Memory Interface Solutions v4.1 only supports the Vivado
®
Design Suite. The ISE
®
Design Suite is not supported in this version.
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