Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 642
UG586 November 30, 2016
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Chapter 4: LPDDR2 SDRAM Memory Interface Solution
CLOCK_DEDICATED_ROUTE Constraints
System Clock
If the SRCC/MRCC I/O pin and PLL are not allocated in the same bank, the
CLOCK_DEDICATED_ROUTE constraint must be set to BACKBONE. LPDDR2 SDRAM manages
these constraints for designs generated with the System Clock option selected as
Differential/Single-Ended (at FPGA Options > System Clock).
If the design is generated with the System Clock option selected as No Buffer (at FPGA
Options > System Clock), the CLOCK_DEDICATED_ROUTE constraints based on the
SRCC/MRCC I/O and PLL allocation needs to be handled manually for the IP flow. LPDDR2
SDRAM does not generate clock constraints in the XDC file for the No Buffer
configurations. You must take care of the clock constraints for the No Buffer configurations
in the IP flow.
Reference Clock
If the SRCC/MRCC I/O pin and MMCM are not allocated in the same bank, the
CLOCK_DEDICATED_ROUTE constraint is set to FALSE. Reference clock is a 200 MHz clock
source used to drive IODELAY CTRL logic (through an additional MMCM). This clock is not
utilized, CLOCK_DEDICADE_ROUTE (as they are limited in number), hence the FALSE value is
1 – B_02 N 15 –
1 CKE B_01 P 14 –
1 A12 B_00 N 13 –
1– A_11P 12 –
1– A_10N 11 –
1A9 A_09 P 10 –
1A8 A_08 N 9 –
1A7 A_07 P 8 DQS-P
1A6 A_06 N 7 DQS-N
1A5 A_05 P 6 –
1A4 A_04 N 5 –
1A3 A_03 P 4 –
1A2 A_02 N 3 –
1A1 A_01 P 2 –
1A0 A_00 N 1 –
1VRN – SE 0 –
Table 4-28: 16-Bit LPDDR2 Interface Contained in One Bank (Cont’d)
Bank Signal Name Byte Group I/O Type I/O Number
Special
Designation
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