Xilinx Zynq-7000 - Page 641

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 641
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Table 4-28: 16-Bit LPDDR2 Interface Contained in One Bank
Bank Signal Name Byte Group I/O Type I/O Number
Special
Designation
1VRP – SE 49 –
1DQ15 D_11 P 48 –
1DQ14 D_10 N 47 –
1DQ13 D_09 P 46 –
1DQ12 D_08 N 45 –
1 DQS1_P D_07 P 44 DQS-P
1 DQS1_N D_06 N 43 DQS-N
1DQ11 D_05 P 42 –
1DQ10 D_04 N 41 –
1DQ9 D_03 P 40 –
1DQ8 D_02 N 39 –
1DM1 D_01 P 38 –
1– D_00N 37 –
1DQ7 C_11 P 36 –
1DQ6 C_10 N 35 –
1DQ5 C_09 P 34 –
1DQ4 C_08 N 33 –
1 DQS0_P C_07 P 32 DQS-P
1 DQS0_N C_06 N 31 DQS-N
1DQ3 C_05 P 30 –
1DQ2 C_04 N 29 –
1 DQ1 C_03 P 28 CCIO-P
1 DQ0 C_02 N 27 CCIO-N
1DM0 C_01 P 26 CCIO-P
1– C_00N 25 –
1 RAS_N B_11 P 24 CCIO-P
1 – B_10 N 23 –
1 – B_09 P 22 –
1 – B_08 N 21 –
1 CK_P B_07 P 20 DQS-P
1 CK_N B_06 N 19 DQS-N
1 – B_05 P 18 –
1 – B_04 N 17 –
1 CS_N B_03 P 16 –
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