Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 131
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
PHY
The PHY provides a physical interface to an external DDR2 or DDR3 SDRAM. The PHY
generates the signal timing and sequencing required to interface to the memory device. It
contains the clock-, address-, and control-generation logic, write and read datapaths, and
state logic for initializing the SDRAM after power-up. In addition, the PHY contains
calibration logic to perform timing training of the read and write datapaths to account for
system static and dynamic delays.
The PHY is provided as a single HDL codebase for DDR2 and DDR3 SDRAMs. The MIG tool
customizes the SDRAM type and numerous other design-specific parameters through
top-level HDL parameters and constraints contained in a XDC file.
Overall PHY Architecture
The 7 series FPGA PHY is composed of dedicated blocks and soft calibration logic. The
dedicated blocks are structured adjacent to one another with back-to-back interconnects to
minimize the clock and datapath routing necessary to build high-performance physical
layers. Dedicated clock structures within an I/O bank referred to as byte group clocks help
minimize the number of loads driven by the byte group clock drivers. Byte group clocks are
driven by phaser blocks. The phaser blocks (PHASER_IN and PHASER_OUT) are multi-stage
programmable delay line loops that can dynamically track DQS signal variation and provide
precision phase adjustment.
Each 7 series FPGA I/O bank has dedicated blocks comprising a PHY control block, four
PHASER_IN and PHASER_OUT blocks, four IN/OUT_FIFOs, IOLOGIC (ISERDES, OSERDES,
ODDR, IDELAY), and IOBs. Four byte groups exist in an I/O bank, and each byte group
contains the PHASER_IN and PHASER_OUT, IN_FIFO and OUT_FIFO, and twelve IOLOGIC and
IOB blocks. Ten of the twelve IOIs in a byte group are used for DQ and DM bits, and the
other two IOIs are used to implement differential DQS signals.
Figure 1-55 shows the dedicated blocks available in a single I/O bank. A single PHY control
block communicates with all four PHASER_IN and PHASER_OUT blocks within the I/O bank.
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