Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 209
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
• DM should be pulled to GND if ODT is used but DM is not driven by the FPGA (for
scenarios where the data mask is not used or is disabled).
I/O Standards
These rules apply to the I/O standard selection for DDR2 SDRAMs:
• Designs generated by the MIG tool use the SSTL18_II_T_DCI and DIFF_SSTL18_II_T_DCI
standards for all bidirectional I/O (DQ, DQS) in the High-Performance banks. In the
High-Range banks, the tool uses the SSTL18_II and DIFF_SSTL18_II standard with the
internal termination (IN_TERM) attribute chosen in the GUI.
• The SSTL18_II and DIFF_SSTL18_II standards are used for unidirectional outputs, such as
control/address and forward memory clocks.
• LVCMOS18 is used for the RESET_N signal driven to the DDR2 memory RDIMM
interfaces. The MIG tool creates the XDC using the appropriate standard based on input
from the GUI.
Trace Lengths
The trace lengths described in this section are for high-speed operation. The package delay
should be included when determining the effective trace length. Different parts in the same
package have different internal package skew values. Derate the minimum period
appropriately in the MIG Controller Options page when different parts in the same
package are used.
One method to determine the delay is to use the L and C values for each pin from the IBIS
models. The delay value is determined as the square root of (L × C).
Another method is to generate the package lengths using Vivado. The following commands
generate a csv file that contains the package delay values for every pin of the device under
consideration.
link_design -part <part_number>
write_csv <file_name>
For example, to obtain the package delay information for the 7 series FPGA
XC7K160T-FF676, this command should be issued:
link_design -part xc7k160tfbg676
write_csv flight_time
This generates a file named flight_time.csv in the current directory with package trace
delay information for each pin. While applying specific trace-matching guidelines for the
DDR2 SDRAM interface, this additional package delay term should be considered for the
overall electrical propagation delay. Different die in the same package might have different
delays for the same package pin. If this is expected, the values should be averaged
appropriately to decrease the maximum possible performance for the target device.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English