Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 451
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
The next step is to increment the fine phase shift delay line of the PHASER_IN block one tap
at a time until a data mismatch is detected. The data read out of IN_FIFO after the required
settling time is then compared with the recorded data at the previous tap value. This is
repeated until a data mismatch is found, indicating detection of a valid data window edge.
Complex pattern read calibration stage is added as the last stage of calibration to improve
margin.
Data Alignment and Valid Generation
This phase of calibration:
• Ensures read data from all the read byte groups is aligned to the rising edge of the
ISERDES CLKDIV capture clock
• Matches the latency for each memory when wider memories are derived from small
memories.
• Sends the determined latency to the read valid generation logic.
After read data capture clock centering is achieved, the calibration logic writes out a known
data pattern to the memory device and issues continuous reads back from the memory. This
is done to determine whether the read data comes back aligned to the positive edge or
negative edge of the ICLKDIV output of the PHASER_IN. This stage of read calibration acts
as feedback to the write calibration state machine (if enabled) to determine the results of a
write for a given byte lane.
For RLDRAM II, captured data from a byte group that is aligned to the negative edge is
made to align to the positive edge using the EDGE_ADV input to the PHASER_IN, which
shifts the ICLKDIV output by one fast clock cycle.
For RLDRAM 3, because the FPGA logic is running at a quarter the rate of the memory clock
frequency, the data is bitslipped in the FPGA logic by a memory clock cycle each time the
pulse is issued to ensure proper alignment of all captured data in the expected order.
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