Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 198
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
• DCI (HP banks) or IN_TERM (HR banks) is required at the FPGA to meet the specified
performance.
•The RESET_N signal is not terminated. This signal should be pulled down during
memory initialization with a 4.7 kΩ resistor connected to GND.
• ODT, which terminates a signal at the memory, is required. The MIG tool should be used
to specify the configuration of the memory system for setting the mode register
properly. See Micron technical note TN-47-01 [Ref 14] for additional details on ODT.
• DM should be pulled to GND if DM is not driven by the FPGA (data mask not used or
data mask disabled scenarios). The value of the pull-down resistor used for DM in this
case should be no larger than four times the ODT value. Check with the memory vendor
for further information.
Trace Lengths
The trace lengths described here are for high-speed operation. The package delay should
be included when determining the effective trace length. Note that different parts in the
same package have different internal package skew values. De-rate the minimum period
appropriately in the MIG Controller Options page when different parts in the same
package are used.
Another method is to generate the package lengths using Vivado Design Suite. The
following commands generate a csv file that contains the package delay values for every
pin of the device under consideration.
link_design -part <part_number>
write_csv <file_name>
For example, to obtain the package delay information for the 7 series FPGA
XC7K160T-FF676, this command should be issued:
link_design -part xc7k160tfbg676
write_csv flight_time
This generates a file named flight_time.csv in the current directory with package trace
delay information for each pin. While applying specific trace-matching guidelines for the
DDR3 SDRAM interface, this additional package delay term should be considered for the
overall electrical propagation delay.
When migrating between different die sizes in the same package, there might be different
delays for the same package pin. The delay values for each of the devices must be
accounted for and the mid-range should be used for each pin. This might decrease the
maximum possible performance for the target device. See Table 1-67 for exact degradation.
These rules indicate the maximum electrical delays between DDR3 SDRAM signals:
• The maximum electrical delay between any DQ or DM and its associated DQS/DQS# must
be ≤ ±5 ps.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English