Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 371
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
10. Decrement the PHASER_IN taps using dbg_pi_f_dec to find the other edge of the
window until another error occurs
(tg_compare_error should be asserted).
11. Record those results, return the PHASER_IN taps to the starting location, and clear the
error again (vio_dbg_clear_error).
This technique uses the error signal that is common for the entire interface, so any
marginality in another bit or byte not being tested might affect the results. For better
results, a per-bit error signal should be used. PHASER_IN taps need to be converted into a
common unit of time to properly analyze the results.
Automated Margin Check
Manually moving taps to verify functionality is useful to check issue bits or bytes, but it can
be difficult to step through an entire interface looking for issues. For this reason, the
QDR II+ SRAM Memory Interface Debug port contains automated window checking that
can be used to step through the entire interface. A state machine is used to take control of
the debug port signals and report results of the margin found per-bit. Currently, the
automated window check only uses PHASER_IN to check window sizes, so depending on the
tap values after calibration, the left edge of the read data window might not be found
properly.
To measure margin with PRBS8 traffic pattern, set VIO signals with the listed values in the
traffic_gen_top instance in example_top:
vio_modify_enable = 'd1
vio_data_mode_value = 'd7
vio_addr_mode_value = 'd3
vio_instr_mode_value = 'd4
vio_bl_mode_value = 'd2
vio_fixed_bl_value = 'd128
vio_fixed_instr_value = 'd1
vio_data_mask_gen = 'd0
Next, assert vio_dbg_clear_error or assert system reset before proceeding with
automated margin check. The steps to follow for automated margin check include:
1. Start automated window check by issuing a single pulse on the VIO signal
dbg_win_start.
2. The VIO signal dbg_win_active indicates that the automated window check is in
progress. The signals dbg_pi_f_inc and dbg_pi_f_dec must not be used when
dbg_win_active is asserted.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English