Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 272
UG586 November 30, 2016
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Interface Debug
AXI4-Lite Interfaces
The AXI4 slave interface follows the AXI4 memory-mapped slave protocol specification as
described in the ARM AMBA open specifications. See this specification [Ref 4] for the
signaling details of the AXI4 slave interface.
Read from a register that does not have all 0s as a default to verify that the interface is
functional. Output s_axi_arready asserts when the read address is valid, and output
s_axi_rvalid asserts when the read data/response is valid. If the interface is
unresponsive, ensure that the following conditions are met:
•The S_AXI_ACLK and ACLK inputs are connected and toggling.
• The interface is not being held in reset, and S_AXI_ARESET is an active-Low reset.
• The interface is enabled, and s_axi_aclken is active-High (if used).
• The main core clocks are toggling and that the enables are also asserted.
• If the simulation has been run, verify in simulation and/or a Vivado logic analyzer
feature waveform debugging tool capture that the waveform is correct for accessing
the AXI4-Lite interface.
AXI4-Stream Interfaces
The AXI4 slave interface follows the AXI4 memory-mapped slave protocol specification as
described in the ARM AMBA open specifications. See this specification [Ref 4] for the
signaling details of the AXI4 slave interface.
If data is not being transmitted or received, check the following conditions:
•If transmit <interface_name>_tready is stuck Low following the
<interface_name>_tvalid input being asserted, the core cannot send data.
•If the receive <interface_name>_tvalid is stuck Low, the core is not receiving
data.
•Check that the ACLK inputs are connected and toggling.
• Check that the AXI4-Stream waveforms are being followed.
• Check core configuration.
• Add appropriate core specific checks.
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