Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 168
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Write Path
The write data is registered in the write FIFO when app_wdf_wren is asserted and
app_wdf_rdy is High (Figure 1-76). If app_wdf_rdy is deasserted, the user logic needs to
hold app_wdf_wren and app_wdf_end High along with the valid app_wdf_data value
until app_wdf_rdy is asserted. app_wdf_data data can be pushed even before app_cmd
"write command" is asserted. The only condition is that for every app_cmd "write
command," the associated app_wdf_data "write data" must be present. The
app_wdf_mask signal can be used to mask out the bytes to write to external memory.
As shown in Figure 1-75, page 167, the maximum delay for a single write between the write
data and the associated write command is two clock cycles.
The app_wdf_end signal must be used to indicate the end of a memory write burst. For
memory burst types of eight in 2:1 mode, the app_wdf_end signal must be asserted on the
second write data word.
The map of the application interface data to the DRAM output data can be explained with
an example.
For a 4:1 Memory Controller to DRAM clock ratio with an 8-bit memory, at the application
interface, if the 64-bit data driven is 0000_0806_0000_0805 (Hex), the data at the DRAM
interface is as shown in Figure 1-78. This is for a Burst Length 8 (BL8) transaction.
X-Ref Target - Figure 1-76
Figure 1-76: 2:1 Mode UI Interface Back-to-Back Write Commands Timing Diagram
(Memory Burst Type = BL8)
X-Ref Target - Figure 1-77
Figure 1-77: 4:1 Mode UI Interface Back-to-Back Write Commands Timing Diagram
(Memory Burst Type = BL8)
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