Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 469
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
• The system clock input must be in the same column as the memory interface. The
system clock input is strongly recommended to be in the address/control bank. If this is
not possible, the system clock input must be in the bank above or below the
address/control bank.
RECOMMENDED: Although the MIG allows system clock selection to be in different super logic regions
(SLRs), it is not recommended due to the additional clock jitter in this topology.
• Devices implemented with SSI technology have SLRs. Memory interfaces cannot span
across SLRs. Ensure that this rule is followed for the part chosen and for any other
pin-compatible parts that can also be used.
RLDRAM 3
In a typical RLDRAM 3 data bank configuration, 9 of these 10 I/Os are used for the data (DQ)
and one can be used for the data mask (DM). The write clocks (DK/DK#) use one of the DQS
pairs inside the Address/Control bank, or the DQS pairs in a free byte lane in a data bank.
QK/QK# clocks must be placed on DQS pins in a given data bank lane associated with this
same clock. Xilinx 7 series FPGAs have dedicated clock routing for high-speed
synchronization that is routed vertically within the I/O banks. Thus, RLDRAM 3 interfaces
must be arranged in the banks vertically and not horizontally. In addition, the maximum
height is three banks.
After a core is generated through the MIG tool, the most optimal pinout has been selected
for the design. Manual changes through the XDC are not recommended. However, if the
XDC needs to be altered, these rules must be taken into consideration:
• The CK/CK# clocks must be placed in an address/control byte lane. CK must be placed
on the P location, and CK# must be placed on the N location, of an I/O pin pair in that
byte lane.
• The DK/DK# clocks must be placed on a DQS pin pair. DK must be placed on the P
location, and DK# must be placed on the N location.
• Data (DQ) is placed such that all signals corresponding to 1-byte (nine bits) are placed
inside a byte group. DQ must not be placed on the DQS N location in a byte lane,
because this location is used for the 3-state control.
• Data Mask (DM) must be placed with one of the corresponding data byte lanes it is
associated with. For the x18 device DM[0] corresponds to DQ[8:0] and DM[1] to
DQ[17:9], while for the x36 device DM[0] corresponds to DQ[8:0]/DQ[26:18] and DM[1]
to DQ[17:9]/DQ[35/27].
RECOMMENDED: If DM pins are not used, they should be tied to ground. For more information, see the
memory vendor data sheet.
• Xilinx recommends keeping all of the data generated from a single memory component
within a bank.
Send Feedback

Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English