Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 632
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
The MIG tool, when available, should be used to generate a pinout for a 7 series LPDDR2
interface. The MIG tool follows these rules:
• DQS signals for a byte group must be connected to a designated DQS CC pair in the
bank.
• DQ signals and a DM signal must be connected to the byte group pins associated with
the corresponding DQS.
• Control (CA, CS_N, CKE) and address lines must be connected to byte groups not used
for the data byte groups.
• All address/control byte groups must be in the same I/O bank. Address/control byte
groups cannot be split between banks.
• The address/control byte groups must be in the middle I/O bank of interfaces that span
three I/O banks.
• CK must be connected to a DQS pair in one of the control byte groups. These pins are
generated for each component and a maximum of four ports/pairs only are allowed
due to I/O pin limitations. Only one CK pair must be connected for one byte group. CK
pairs are generated for each component, and a maximum of four pairs only are allowed
due to I/O pin limitations. This varies based on Memory Clock Selection in the
Memory Options page in the MIG GUI. Except CK/CK#, any of the Address/Control pin
should not be allocated to DQS.
• CS_N pins are generated for each component and a maximum of four ports/pairs only
are allowed due to I/O pin limitations.
•Only one CKE port is generated.
• VRN and VRP are used for the digitally controlled impedance (DCI) reference for banks
that support DCI. DCI cascade is permitted.
• The interface must be arranged vertically.
• No more than three banks can be used for a single interface. All the banks chosen must
be consequent.
• The system clock input must be in the same column as the memory interface. The
system clock input is recommended to be in the address/control bank, when possible
RECOMMENDED: Although the MIG allows system clock selection to be in different super logic regions
(SLRs), it is not recommended due to the additional clock jitter in this topology.
• Devices implemented with SSI technology have SLRs. Memory interfaces cannot span
across SLRs. Ensure that this rule is followed for the part chosen and for any other
pin-compatible parts that can also be used.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English