Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 138
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Table 1-59: Auxiliary Output Attributes
Attribute Type Description
MC_AO_WRLVL_EN Vector[3:0]
This attribute specifies whether or not the related Aux_Output is active
during write leveling as specified by the PC_Enable_Calib[1] signal. For
example, this attribute specifies whether ODT is active during write
leveling.
WR_CMD_OFFSET_0 Vector[5:0]
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
after the associated write command is executed that the auxiliary output
becomes active. For example, this attribute ensures that the ODT signal
is asserted at the correct clock cycle to meet the JEDEC ODTLon and
ODTLoff specifications.
WR_DURATION_0 Vector[5:0]
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
the auxiliary output remains active for a write command. For example,
this attribute ensures that the ODT signal is asserted at the correct clock
cycle to meet the JEDEC ODTLon and ODTLoff specifications.
RD_CMD_OFFSET_0 Vector[5:0]
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
after the associated read command is executed that the auxiliary output
becomes active.
RD_DURATION_0 Vector[5:0]
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
the auxiliary output remains active for a read command.
WR_CMD_OFFSET_1 Vector[5:0]
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
after the associated write command is executed that the auxiliary output
becomes active.
WR_DURATION_1 Vector[5:0]
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
the auxiliary output remains active for a write command.
RD_CMD_OFFSET_1 Vector[5:0]
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
after the associated read command is executed that the auxiliary output
becomes active.
RD_DURATION_1 Vector[5:0]
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
the auxiliary output remains active for a read command.
WR_CMD_OFFSET_2 Vector[5:0]
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
after the associated write command is executed that the auxiliary output
becomes active.
WR_DURATION_2 Vector[5:0]
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
the auxiliary output remains active for a write command.
RD_CMD_OFFSET_2 Vector[5:0]
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
after the associated read command is executed that the auxiliary output
becomes active.
RD_DURATION_2 Vector[5:0]
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
the auxiliary output remains active for a read command.
WR_CMD_OFFSET_3 Vector[5:0]
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
after the associated write command is executed that the auxiliary output
becomes active.
WR_DURATION_3 Vector[5:0]
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
the auxiliary output remains active for a write command.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English