Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 141
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
The timing diagram of the address/command path from the output of the OUT_FIFO to the
FPGA pins is shown in Figure 1-59.
X-Ref Target - Figure 1-58
Figure 1-58: Address/Command Path Block Diagram
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English