EasyManuals Logo
Home>Xilinx>Motherboard>Zynq-7000

Xilinx Zynq-7000 User Manual

Xilinx Zynq-7000
678 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #176 background imageLoading...
Page #176 background image
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 176
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
X-Ref Target - Figure 1-88
Figure 1-88: PHY Interface Example
$$2
3$2!-
0HYSICAL,AYER)NTERFACE
-#?2!3?.
-#?#!3?.
-#?7%?.
-#?#3?.
-#?"!;=
-#?!$$2%33;=
&2%1?2%&#,+
-#?#-$;=
-#?#-$?72%.
0(9?-#?#-$?&5,,
-#?#4,?72%.
0(9?-#?#4,?&5,,
-#?#-$;=
#!,)"?2$?$!4!?/&&3%4
-#?72$!4!;N=
-#?72$!4!?%.
-#?72$!4!?-!3+;N=
0(9?-#?$!4!?&5,,
0(9#ONTROL
!DDRESS#OMMAND
/54?&)&/
7RITE$ATA
/54?&)&/
2EAD$ATA
).?&)&/
0(9?2$?$!4!
0(9?2$$!4!?6!,)$
-%-?2%&#,+
#,+
#,+?2%&
39.#?05,3%
).)4?#!,)"?#/-0,%4%
234
0,,?,/#+
)/,/')#
$1BUS
$-
$13
!DDR#MD#ONTROL
#LOCKS
-#?2%334?.
$$2?234?.
-#?2!.+?#.4;=
-#?#!3?3,/4;=
0(9#ONTROL7ORD
0(9#ONTROL7ORDCOMPOSEDOF
-#?!58?/54;=
-#?$!4!?/&&3%4;=
#ONTROL/FFSET;=TIETOINTERNALLY
!CT0RETIETOINTERNALLY
%VENT$ELAY;=TIETOINTERNALLY
,OW)NDEX;=TIETOINTERNALLY
3EQ;=TIETOINTERNALLY
?? ?
??
8
Send Feedback

Table of Contents

Other manuals for Xilinx Zynq-7000

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Xilinx Zynq-7000 and is the answer not in the manual?

Xilinx Zynq-7000 Specifications

General IconGeneral
BrandXilinx
ModelZynq-7000
CategoryMotherboard
LanguageEnglish

Related product manuals