Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 259
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
• If this stage of calibration was successful and the results need to be analyzed, set the
ILA trigger to dbg_rdlvl_done[0] = R.
• Set the VIO dbg_dqs for each byte and capture the following signals. The results for
each byte should be captured in the “7 Series DDR3 Calibration Results” spreadsheet.
Later releases of the MIG tool include results for all DQS byte groups removing the
need to use dbg_dqs.
• Determine which stage is failing by observing cal1_state_r.
• Look at idelay_tap_cnt for each byte group. The idelay_tap_cnt across the DQS
byte groups should only vary by 2 to 3 taps.
Table 1-80: Debug Signals of Interest for Read Leveling Stage 1 Calibration
Signal Name Description
dbg_rdlvl_start[0] Signifies the start of Read Leveling Stage 1 of calibration.
dbg_rdlvl_done[0]
Signifies the successful completion of Read Leveling Stage 1 of
calibration.
dbg_rdlvl_err[0]
Signifies Read Leveling Stage 1 of calibration exhibited errors and
did not complete.
cal1_state_r
State machine variable for MPR and Read Leveling Stage 1. States
can be decoded in the ddr_phy_rdlvl.v module.
cal1_cnt_cpt_r
Signifies the byte that failed MPR read leveling or read leveling
stage 1.
dbg_cpt_first_edge_cnt_by_dqs
Signifies PHASER_IN fine tap count when the first edge in MPR and
Read Leveling Stage 1 is found. Byte capture based on VIO dbg_dqs
setting.
dbg_cpt_first_edge_cnt
Signifies PHASER_IN fine tap count when the first edge in MPR and
Read Leveling Stage 1 is found.
dbg_cpt_second_edge_cnt_by_dqs
Signifies PHASER_IN fine tap count when then second edge in MPR
and Read Leveling Stage 1 is found. Byte capture based on VIO
dbg_dqs setting.
dbg_cpt_second_edge_cnt
Signifies PHASER_IN fine tap count when then second edge in MPR
and Read Leveling Stage 1 is found.
dbg_cpt_tap_cnt_by_dqs
Signifies the center tap moved to based on when the first and
second edges were found. Byte capture based on VIO dbg_dqs
setting.
dbg_cpt_tap_cnt
Signifies the center tap moved to based on when the first and
second edges were found.
dbg_dq_idelay_tap_cnt_by_dqs
IDELAY tap value for MPR and Read Leveling Stage 1. This should be
within 2 to 3 taps across all DQS byte groups. Byte capture based
on VIO dbg_dqs setting.
dbg_dq_idelay_tap_cnt
IDELAY tap value for MPR and Read Leveling Stage 1. This should be
within 2 to 3 taps across all DQS byte groups.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English