Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 442
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Note: The overall read latency of the MIG 7 series RLDRAM II/RLDRAM 3 core is dependent on how
the Memory Controller is configured, but most critically on the target traffic/access pattern and the
number of commands already in the pipeline before the read command is issued. Read latency is
measured from the point where the read command is accepted by the user or native interface.
Simulation should be run to analyze read latency.
X-Ref Target - Figure 3-48
Figure 3-48: High-Level PHY Block Diagram of the RLDRAM II/RLDRAM 3 Interface Solution
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English